1. Field of the Invention
The present invention relates to a semiconductor circuit pattern design method for manufacturing a semiconductor device or liquid crystal display device, a computer program product for pattern design, and a method of manufacturing a semiconductor device or liquid crystal display device.
2. Description of the Related Art
Along with the recent remarkable progress of semiconductor manufacturing technologies, semiconductor elements with a minimum line width of 0.1 μm or less have been mass-produced. This microfabrication is implemented by dramatic improvements of micropattern formation technologies and various EDA tools for circuit pattern generation.
In an era of sufficiently large pattern sizes, the planar shape of an LSI pattern to be formed on a wafer was directly formed as a design pattern, and a mask pattern faithfully complying with the design pattern was created. The mask pattern was transferred onto a wafer by using a projecting optical system, and the underlying layers were etched. In this way, a pattern that was almost the same as the design pattern could be formed on the wafer. However, as the pattern size decreases, it is becoming difficult to faithfully form a pattern in each process, and the final finished dimensions differ from the dimensions of the design pattern.
Especially in lithography and etching processes which are most important for achieving microfabrication, the layout environment of other patterns placed around a pattern to be formed greatly influences the dimensional accuracy of the pattern. As techniques of reducing the influence, optical proximity correction (OPC) and process proximity correction (PPC) have been reported, which add an assist pattern to the design pattern in advance such that the desired pattern is reflected on the dimensions after working (e.g., Jpn. Pat. Appln. KOKAI Publication No. 9-319067 and D. M. Newmark et al., “Large Area Optical Proximity Correction using Pattern Based Correction”, SPIE Vol. 2322 (1994), p. 374).
From the viewpoint of performance, currently, intra-cell and routing layouts are designed such that timing margins are satisfied. Hence, cells with an unreasonable driving force are used to obtain a transistor operation speed within the margin. Serious problems also arise because the chip area increases as a result of buffer insertion, and the load on iteration increases due to timing closure by transistors designed in dimensions of worst conditions.
Presently, since the design pattern created by the designer largely differs from the mask pattern used for exposure because of the complex OPC and PPC technologies, the finished pattern shape on the wafer can hardly be predicted. For this reason, verification using a process simulator must be executed for the design pattern prior to shipping the design pattern, i.e., ending creation of the design pattern. However, lithography verification is done in the final stage of design process. Feeding back the verification result indicates regress in the design step, which places a heavy load on the turnaround time of the design pattern creation step.
As described above, in the conventional pattern design method, it is not easy to predict the finished pattern shape on the wafer because the OPC and PPC technologies are complex. Hence, the load on timing closure on the design side and the load on OPC and process verification on the manufacture side increase.